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AM5716AABCDA 데이터시트(PDF) 5 Page - Texas Instruments

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부품명 AM5716AABCDA
상세설명  Sitara Processors Silicon Revision 2.0
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제조업체  TI1 [Texas Instruments]
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AM5718, AM5716
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SPRS957D – MARCH 2016 – REVISED JANUARY 2017
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Revision History
Copyright © 2016–2017, Texas Instruments Incorporated
2
Revision History
Changes from August 1, 2016 to January 20, 2017 (from B Revision (August 2016) to D Revision)
Page
Updated features list and block diagram
.......................................................................................... 1
Added conformity to AEC-Q100 Standard in Section 1.3
....................................................................... 2
Added link for AM57xx family Parametric table in Section 3.1
................................................................. 6
Added device hex codes to Table 3-1
............................................................................................. 6
Updated column description parameter [4] in Section 4.2
..................................................................... 11
Updated DSIS Description for "blank" in Section 4.2
........................................................................... 12
Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 4-30
...................................... 134
Added conformity to Q100 Standard in Table 5-2 and updated Table 5-4, and Table 5-5
.............................. 141
Fixed typos and clean-up in Table 5-5
.......................................................................................... 142
Updated rstoutn timing in Figure 5-1
............................................................................................ 176
Updated Figure 5-1 and Figure 5-2 to allow either non-RTC or RTC PMIC implementations
........................... 176
Updated Power down sequences footnote under Figure 5-2
................................................................ 179
Added DSS_VIRTUAL1 and MMC2_VIRTUAL2 options to the Timing Chapter Section 7
.............................. 196
Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 7-2
........................................ 196
Added new timing information for VIP, DSS VOUT, GPMC, McSPI, QSPI, McASP and Ethernet Interfaces
........ 199
Added missing balls for vin1b in IOSET7 in Table 7-4
....................................................................... 200
Updated Manual Modes for VIP, DSS, MMC and PRU-ICSS Interfaces
................................................... 207
Updated are Virtual Mode Case Details for McASP2 when AXR(Inputs)/CLKX/FSX in 80MHz and non-80MHz
operation.
.......................................................................................................................... 276
Fixed typo in naming of figures McASP1-8 for SYNC Mode in Table 7-59
................................................ 284
Removed 1149.7 (cJTAG) support from the AM571x family of devices
.................................................... 357
Updated broken note in High-Speed Bypass Capacitors Table 8-10
....................................................... 367
Updated symbolization in Printed Device Reference Figure 9-1 and Nomenclature Description Table 9-1
........... 388
Added conformity to Q100 Standard by updating Figure 9-1 and Table 9-1
.............................................. 388


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