전자부품 데이터시트 검색엔진 |
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74LVC1G3157DRLRG4 데이터시트(PDF) 8 Page - Texas Instruments |
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74LVC1G3157DRLRG4 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 40 page 8 SN74LVC1G3157 SCES424L – JANUARY 2003 – REVISED MAY 2017 www.ti.com Product Folder Links: SN74LVC1G3157 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated (1) Set fin to 0 dBm and provide a bias of 0.4 V. Increase fin frequency until the gain is 3 dB below the insertion loss. (2) Set fin to 0 dBm and provide a bias of 0.4 V. 6.6 Analog Switch Characteristics TA = 25°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC TYP UNIT Frequency response(1) (switch on) A or Bn Bn or A RL = 50 Ω, fin = sine wave (see Figure 6) 1.65 V 340 MHz 2.3 V 340 3 V 340 4.5 V 340 Crosstalk(2) (between switches) B1 or B2 B2 or B1 RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 7) 1.65 V –54 dB 2.3 V –54 3 V –54 4.5 V –54 Feed through attenuation(2) (switch off) A or Bn Bn or A CL = 5 pF, RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 8) 1.65 V –57 dB 2.3 V –57 3 V –57 4.5 V –57 Charge injection S A CL = 0.1 nF, RL = 1 MΩ (see Figure 9) 3.3 V 3 pC 5 V 7 Total harmonic distortion A or Bn Bn or A VI = 0.5 Vp-p, RL = 600 Ω, fin = 600 Hz to 20 kHz (sine wave) (see Figure 10) 1.65 V 0.1% 2.3 V 0.025% 3 V 0.015% 4.5 V 0.01% |
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