 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
73K324L-IP 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers |
|
||||||||||||||||||||||||||||||
73K324L-IP 데이터시트(HTML) 8 Page - List of Unclassifed Manufacturers |
|
|
8 / 31 page  73K324L CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem 8 CONTROL REGISTER 0 D7 D6 D5 D4 D3 D2 D1 D0 CR0 000 MODUL. OPTION MODUL. TYPE 1 MODUL. TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE BIT NO. NAME CONDITION DESCRIPTION 0 Selects Answer mode (transmit in high band, receive in low band) or in V.23 HDX mode, receive at 1200 bit/s and transmit at 75 bit/s. 1 Selects Originate mode (transmit in low band,receive in high band) or in V.23 HDX mode, receive at 75 bit/s and transmit at 1200 bit/s. D0 Answer/ Originate Note: This bit works with Tone Register bits D0 and D6 to program special tones detected in the Detect Register. See Detect and Tone Registers. 0 Disables transmit output at TXA. 1 Enables transmit output at TXA. D1 Transmit Enable Note: Transmit Enable must be set to 1 to allow activation of Answer Tone, DTMF, or Carrier. D5 D4 D3 D2 0 0 0 0 Selects Power Down mode. All functions are disabled except the digital interface. 0 0 0 1 Internal Synchronous mode. In this mode TXCLK is an internally derived 600, 1200 or 2400 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. 0 0 1 0 External Synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be supplied externally. 0 0 1 1 Slave Synchronous mode. Same operation as other Synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. 0 1 0 0 Selects Asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). 0 1 0 1 Selects Asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). 0 1 1 0 Selects Asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). 0 1 1 1 Selects Asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and/or 1 or 2 stop bits). D5, D4, D3, D2 Transmit Mode 1 X 0 0 Selects FSK operation. |
유사한 부품 번호 - 73K324L-IP |
|
유사한 설명 - 73K324L-IP |
|
|
링크 URL |
| 개인정보취급방침 |
| ALLDATASHEET.CO.KR |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
