LM3641

Lithium-Ion Battery Pack Protection Circuit

General Description

The LM3641 Lithium Protection Integrated Circuit resides in-

side a 3.6V Lithium-Ion battery pack consisting of a single

cell or multiple parallel cells. The IC controls the ON/OFF

state of a pair of low threshold N-channel power MOSFETs

placed in series with the battery cell(s). The purpose of this

MOSFET pair is to protect the cell(s) from inadvertent elec-

trical over-stress. The IC compares the cell voltage against

internally programmed minimum and maximum limits. Tran-

sient voltage faults of approximately 1.25 seconds are toler-

ated.

The IC also monitors the bi-directional current flow in the bat-

tery pack by measuring the voltage across a robust 4 m

Ω

current sensing resistor internal to the protection IC pack-

age. The IC turns OFF the MOSFET pair whenever any fault

erated.

The Enable pin allows external ON/OFF control of the MOS-

FET pair and resets the IC after the MOSFET pair is turned

OFF and the pack is safe to operate again.

The limits for overcharge and overdischarge voltage, as well

as independent limits for each direction of overcurrent are

factory adjusted employing EEPROM.

Features

n Automatic battery disconnect when the cell is

over-charged or over-discharged.

n Maximum cell voltage for MOSFET conduction is factory

tolerance (0˚C to +60˚C).

n Minimum cell voltage for MOSFET conduction =

0.57

•V

n Internal 4 m

maximum accuracy for detection of overcurrent faults.

The maximum charge and discharge current is factory

programmable between 1A and 5A. A single overcurrent

fault event opens and protects the MOSFET pair.

n Automatic detection of safe pack conditions for recovery

(MOSFET pair ON) from a fault condition (over/under

discharged or overcurrent).

n Average current drain = 1.2 µA typical.

n Optional Enable pack terminal can be used to prevent

accidental short circuit of pack and for maximizing the

shelf life of the pack (IC powers down when the pack is

not in use).

n Over-current events cause connection of an internal

50 k

Ω “FET-Bypass” resistance across OFF MOSFET

Ω are required for return to

conduction mode.

n Over-charged states cause connection ofa5k

Ω

“Cell-Bypass” resistor to ensure that the cell is not

allowed to be overcharged by leakage paths.

Typical Application

DS012931 1

January 1999

© 1999 National Semiconductor Corporation

DS012931

www.national.com