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CD54HC4049 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Texas Instruments

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๋ถ€ํ’ˆ๋ช… CD54HC4049
์ƒ์„ธ๋‚ด์šฉ  High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting
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CD54HC4049 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Texas Instruments

   
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4
Quiescent Device
Current
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
ยตA
DC Electrical Speci๏ฌcations (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
โ€“40oC TO 85oC
โ€“55oC TO
125oC
UNITS
VI (V)
IO (mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Switching Speci๏ฌcations Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
โ€“40oC TO
85oC
โ€“55oC TO
125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
tPLH, tPHL
CL = 50pF
2
-
-
85
-
105
-
130
ns
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
CL = 15pF
5
-
6
-
-
-
-
-
ns
Transition Times (Figure 1)
tTLH, tTHL
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 2, 3)
CPD
-5
-
35
-
-
-
-
-
pF
NOTES:
2. CPD is used to determine the dynamic power consumption, per gate.
3. PD = VCC
2 f
i (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuit and Waveform
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050


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