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CS5529-AS 데이터시트(PDF) 1 Page - Cirrus Logic |
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1 / 30 page 1 Copyright © Cirrus Logic, Inc. 1999 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CS5529 16-Bit, Programmable ∆Σ ADC with 6-Bit Latch Features l Delta-Sigma Analog-to-Digital Converter - Linearity Error: 0.0015%FS - Noise Free Resolution: 16-Bits l 2.5 V Bipolar/Unipolar Buffered Input Range l 6-Bit Output Latch l Eight Digital Filters - Selectable Output Word Rates - Output Settles in One Conversion Cycle - 50/60 Hz ±3 Hz Simultaneous Rejection l Simple three-wire serial interface - SPI™ and Microwire™ Compatible - Schmitt Trigger on Serial Clock (SCLK) l System/Self-Calibration with R/W Registers l Power Supply Configurations - VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V - VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V l Low Power Consumption: 2.5 mW General Description The 16-bit CS5529 is a low-power programmable ∆Σ An- alog-to-Digital Converter (ADC) which includes coarse/fine charge buffers, a fourth order ∆Σ modulator, a calibration microcontroller, a digital filter with program- mable decimation rates, a 6-bit output latch, and a three- wire serial interface. The ADC is designed to operate from single or dual analog supplies and a single digital supply. The digital filter is programmable with output update rates between 1.88 Hz to 101 Hz. These output rates are specified for XIN = 32.768 kHz. Output word rates can be increased by approximately 3X by using XIN = 100 kHz. The filter is designed to settle to full accuracy for the se- lected output word rate in one conversion. When operated at word rates of 15 Hz or less, the filter rejects both 50 Hz and 60 Hz simultaneously. Low power, single conversion settling time, programma- ble output rates, and the ability to handle negative input signals make this single or dual supply product an ideal solution for isolated and non-isolated applications. ORDERING INFORMATION See page 27. VA+ AIN+ AIN- VREF+ VREF- Latch A0 A1 D0 D1 D2 D3 Calibration Memory Calibration µC Clock Gen. XIN XOUT VA- DGND 1X 1X Differential 4th Order Delta-Sigma Modulator Digital Filter Calibration Register Control Register Output Register VD+ CS SCLK SDI SDO MAR ‘99 DS246F1 |
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