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TC55VBM316AFTN ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 10 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC55VBM316AFTN
์ƒ์„ธ๋‚ด์šฉ  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.semicon.toshiba.co.jp/eng
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TC55VBM316AFTN ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 10 Page - Toshiba Semiconductor

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TC55VBM316AFTN/ASTN40,55
2002-08-05
10/15
WRITE CYCLE 4 (
,
CONTROLLED)
(See Note 4)
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the
outputs will remain at high impedance.
(3)
If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
UB LB
R/W
tWC
tAS
tWR
tWP
1
CE
VALID DATA IN
tDS
tDH
Hi-Z
Hi-Z
tCW
CE2
tBW
tBE
tCOE
tODW
UB
, LB
tCW
(See Note 5)
Address
A0~A18 (Word Mode)
DOUT
I/O1~16 (Word Mode)
DIN
I/O1~16 (Word Mode)


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