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TC58512FT ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC58512FT
์ƒ์„ธ๋‚ด์šฉ  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
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TC58512FT ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Toshiba Semiconductor

 
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TC58512FT
2001-03-05
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Note: (1) CE High to Ready time depends on the pull-up resistor tied to the
BY
/
RY
pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns,
BY
/
RY
signal stays Ready.
PROGRAMMING AND ERASING CHARACTERISTICS (Ta
==== 0ยฐ to 70ยฐC, VCC ==== 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
tPROG
Programming Time
ยพ
200
1000
ms
tDBSY
Dummy Busy Time for Multi Block
Programming
ยพ
2
10
ms
tMBPBSY
Multi Block Program Busy Time
ยพ
200
1000
ms
N
Number of Programming Cycles on Same
Page
ยพ
ยพ
3
(1)
tBERASE
Block Erasing Time
ยพ
2
10
ms
(1): Refer to Application Note (12) toward the end of this document.
: 0 to 30 ns
ยฎ Busy signal is not output.
A
CE
RE
tCEH ยณ 100 ns
*
525
Busy
BY
/
RY
*: VIH or VIL
A
526
527
tCRY


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