TC58512FT datasheet(21/43 Pages) TOSHIBA

부품명	TC58512FT

상세설명	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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제조업체	TOSHIBA [Toshiba Semiconductor]

홈페이지	http://www.semicon.toshiba.co.jp/eng

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21 / 43 page

TC58512FT

2001-03-05

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Schematic Cell Layout and Address Assignment

The Program operation works on page units while the Erase operation works on block units.

A page consists of 528 bytes in which 512 bytes are used for

main memory storage and 16 bytes are for redundancy or for

other uses.

1 page = 528 bytes

1 block = 528 bytes ´ 32 pages = (16K + 512) bytes

Capacity = 528 bytes ´ 32 pages ´ 4096 blocks

An address is read in via the I/O port over four consecutive

clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

First cycle

A7

A6

A5

A4

A3

A2

A1

A0

Second cycle

A16

A15

A14

A13

A12

A11

A10

A9

Third cycle

A24

A23

A22

A21

A20

A19

A18

A17

Fourth cycle

*L

A25

A0 to A7

: Column address

A9 to A25 : Page address

A14 to A25 : Block address

A9 to A13 : NAND address in block

* : A8 is automatically set to Low or High by a 00H command or a 01H command.

* : l/O2 to l/O8 must be set to Low in the fourth cycle.

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by the fourteen different

command operations shown in Table 3. Address input, command input and data input/output are controlled by

the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.

Table 2. Logic Table

CLE

ALE

CE

WE

RE

WP

Command Input

H

L

H

*

Data Input

L

H

*

Address Input

L

H

L

H

*

Serial Data Output

L

H

*

During Programming (Busy)

*

H

During Erasing (Busy)

*

H

Program, Erase Inhibit

*

L

H: VIH, L: VIL, *: VIH or VIL

16

512

I/O1

I/O8

8I/O

528

131072 pages

4096 blocks

Figure 2. Schematic Cell Layout

32 pages

1 block

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