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M4TKVG6AE 데이터시트(PDF) 6 Page - List of Unclassifed Manufacturers

부품명 M4TKVG6AE
상세설명  32-bit Microcontroller
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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M4TK
Jan. 06, 2016
Page 6 of 144
Rev.1.00
List of Figures
Figure 4.1-1 NuMicro
® M4TK Selection Code.................................................................................................... 18
Figure 4.2-1 NuMicro
® M4TK CAN Series (CAN+USB) LQFP 48-pin Diagram................................................. 20
Figure 4.2-2 NuMicro
® M4TK CAN Series (CAN+USB) LQFP 64-pin Diagram................................................. 21
Figure 4.2-3 NuMicro
® M4TK CAN Series (CAN+USB) LQFP 100-pin Diagram............................................... 22
Figure 5.1-1 NuMicro
® M4TK Block Diagram..................................................................................................... 60
Figure 6.1-1 Cortex
® -M4 Block Diagram ............................................................................................................ 61
Figure 6.2-1 System Reset Sources .................................................................................................................. 65
Figure 6.2-2 nRESET Reset Waveform ............................................................................................................. 68
Figure 6.2-3 Power-on Reset (POR) Waveform ................................................................................................ 68
Figure 6.2-4 Low Voltage Reset (LVR) Waveform ............................................................................................. 69
Figure 6.2-5 Brown-out Detector (BOD) Waveform ........................................................................................... 70
Figure 6.2-6 Power Mode State Machine........................................................................................................... 71
Figure 6.2-7 NuMicro
® M4TK Power Distribution Diagram ................................................................................ 74
Figure 6.2-8 SRAM Block Diagram .................................................................................................................... 78
Figure 6.2-9 SRAM Memory Organization ......................................................................................................... 79
Figure 6.3-1 Clock Generator Global View Diagram .......................................................................................... 83
Figure 6.3-2 Clock Generator Block Diagram .................................................................................................... 84
Figure 6.3-3 System Clock Block Diagram......................................................................................................... 85
Figure 6.3-4 HXT Stop Protect Procedure ......................................................................................................... 86
Figure 6.3-5 SysTick Clock Control Block Diagram ........................................................................................... 86
Figure 6.3-6 Clock Source of Clock Output........................................................................................................ 87
Figure 6.3-7 Clock Output Block Diagram .......................................................................................................... 88
Figure 8.3-1 Typical Crystal Application Circuit ............................................................................................... 122
Figure 8.3-2 HIRC Accuracy vs. Temperature ................................................................................................. 122
Figure 8.3-3 Typical Crystal Application Circuit ............................................................................................... 124
Figure 8.4-1 Typical connection diagram using the ADC................................................................................. 126
Figure 8.4-2 Power-up Ramp Condition........................................................................................................... 128
Figure 8.6-1 I
2C Timing Diagram...................................................................................................................... 133
Figure 8.7-1 SPI Master Mode Timing Diagram............................................................................................... 134
Figure 8.7-2 SPI Slave Mode Timing Diagram................................................................................................. 136
Figure 8.8-1 I
2S Master Mode Timing Diagram................................................................................................ 138
Figure 8.8-2 I
2S Slave Mode Timing Diagram.................................................................................................. 138


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