전자부품 데이터시트 검색엔진 |
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KM681001B-15 데이터시트(PDF) 6 Page - Samsung semiconductor |
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KM681001B-15 데이터시트(HTML) 6 Page - Samsung semiconductor |
6 / 9 page KM681001B CMOS SRAM PRELIMINARY Rev 2.0 - 6 - February 1998 NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS1=VIL and CS2=VIH. 7. Address valid prior to coincident with CS1 transition low and CS2 transition high. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) Address CS1 CS2 tWP(2) tDW tDH Valid Data WE Data in Data out tWC tWR(5) tAW tCW(3) High-Z(8) High-Z OE tOHZ(6) tAS(4) TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) CS1 Address OE Data out CS2 tAA tOLZ tLZ(4,5) tOH tOHZ tRC tOE tCO tPU tPD Valid Data tHZ(3,4,5) 50% 50% VCC Current ICC ISB |
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유사한 설명 - KM681001B-15 |
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