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GS82582Q18GE-250 데이터시트(PDF) 7 Page - GSI Technology

부품명 GS82582Q18GE-250
상세설명  288Mb SigmaQuad-IITM Burst of 2 SRAM
Download  32 Pages
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS82582Q18GE-250 데이터시트(HTML) 7 Page - GSI Technology

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GS82582Q18/36GE-357/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2016
7/31
© 2012, GSI Technology
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Unchanged
Written
Beat 1
Beat 2
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.


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