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MC33996 데이터시트(PDF) 7 Page - Motorola, Inc

부품명 MC33996
상세설명  16-Output Switch with SPI Control
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC33996 데이터시트(HTML) 7 Page - Motorola, Inc

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
7
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V
≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
RL = 56 Ω (Note 16)
SR
1.0
2.0
10
V/
µs
Output Turn ON Delay Time (Note 17)
tDLY(on)
1.0
15
50
µs
Output Turn OFF Delay Time (Note 17)
tDLY(off)
1.0
15
50
µs
Output ON Short Fault Disable Report Delay (Note 18)
tDLY(short)
100
450
µs
Output OFF Open Fault Delay Time (Note 18)
tDLY(open)
100
450
µs
Output PWM Frequency
tFREQ
2.0
kHz
DIGITAL INTERFACE TIMING
Required Low State Duration on VPWR for Reset
VPWR ≤ 0.2 V (Note 19)
tRST
10
µs
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
tLEAD
100
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
tLAG
50
ns
SI to Falling Edge of SCLK
Required Setup Time
tSI(su)
16
ns
Falling Edge of SCLK to SI
Required Hold Time
tSI(hold)
20
ns
SI, CS, SCLK Signal Rise Time (Note 20)
tR(SI)
5.0
ns
SI, CS, SCLK Signal Fall Time (Note 20)
tF(SI)
5.0
ns
Time from Falling Edge of CS to SO Low Impedance (Note 21)
tSO(en)
50
ns
Time from Rising Edge of CS to SO High Impedance (Note 22)
tSO(dis)
50
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 23)
tVALID
25
80
ns
Notes
16.
Output slew rate measured across a 56
Ω resistive load.
17.
Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
18.
Duration of fault before fault bit is set. Duration between access times must be greater than 450
µs to read faults.
19.
This parameter is guaranteed by design; however, it is not production tested.
20.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
21.
Time required for valid output status data to be available on SO pin.
22.
Time required for output states data to be terminated at SO pin.
23.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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