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DLP650NEFYE 데이터시트(PDF) 5 Page - Texas Instruments |
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DLP650NEFYE 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 44 page 5 DLP650NE www.ti.com DLPS097 – AUGUST 2017 Product Folder Links: DLP650NE Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN(1) TYPE (2) SIGNAL DATA RATE(3) INTERNAL TERM (4) DESCRIPTION TRACE (mils)(5) NAME NO. SERIAL CONTROL SCTRL_AN C23 I LVDS DDR Differential Serial control, negative 492.95 SCTRL_BN Y23 I DDR Differential Serial control, negative 493.78 SCTRL_AP C24 I DDR Differential Serial control, negative 493.78 SCTRL_BP Y24 I DDR Differential Serial control, negative 493.11 CLOCKS DCLK_AN B23 I LVDS Differential Clock, negative 480.35 DCLK_BN Z23 I Differential Clock, negative 486.22 DCLK_AP B22 I Differential Clock, negative 485.83 DCLK_BP Z22 I Differential Clock, negative 491.93 SERIAL COMMUNICATIONS PORT (SCP) SCP_DO B8 O LVCMOS SDR Serial communications port output SCP_DI B7 I SDR Pull-Down Serial communication port data I SCP_CLK B6 I Serial communications port clock SCP_ENZ C8 I Active-low serial communications port enable MICROMIRROR RESET CONTROL RESET_ADDR(0) X9 I LVCMOS Pull-Down Reset driver address select RESET_ADDR(1) X8 I Reset driver address select RESET_ADDR(2) Z8 I Reset driver address select RESET_ADDR(3) Z7 I Reset driver address select RESET_MODE(0) W11 I Reset driver mode select RESET_MODE(1) Z10 I Reset driver mode select RESET_SEL(0) Y10 I Reset driver level select RESET_SEL(1) Y9 I Reset driver level select RESET_STROBE Y7 I Reset address, mode, and level latched on rising-edge ENABLES & INTERRUPTS PWRDNZ D2 I LVCMOS Pull-Down Active-low device reset RESET_OEZ W7 I Pull-Down Active-low output enable for DMD reset driver circuits RESETZ Z6 I Pull-Down Active-low sets reset circuits in known VOFFSET state RESET_IRQZ Z5 O Active-low, output interrupt to ASIC VOLTAGE REGULATOR MONITORING PG_BIAS E11 I LVCMOS Pull-Up Active-low fault from external VBIAS regulator PG_OFFSET B10 I Active-low fault from external VOFFSET regulator PG_RESET D11 I Active-low from external VRESET regulator EN_BIAS D9 O Active-high enable for external VBIAS regulator EN_OFFSET C9 O Active-high enable for external VOFFSET regulator EN_RESET E9 O Active-high enable for external VRESET regulator |
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