GS8673ED18/36BK-675/625/550/500

72Mb SigmaQuad-IIIe™

Burst of 4 ECCRAM™

675 MHz–500 MHz

Rev: 1.06 5/2012

1/31

© 2011, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

260-Ball BGA

Commercial Temp

Industrial Temp

Features

• On-Chip ECC with virtually zero SER

• Configurable Read Latency (3.0 or 2.0 cycles)

• Simultaneous Read and Write SigmaQuad-IIIe™ Interface

• Separate I/O Bus

• Double Data Rate interface

• Burst of 4 Read and Write

• Pipelined read operation

• Fully coherent Read and Write pipelines

• 1.2V JESD8-16A BIC-3 Compliant Interface

• 1.5V HSTL Interface

• ZQ pin for programmable output drive impedance

• ZT pin for programmable input termination impedance

• Configurable Input Termination

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package

–K: 5/6 RoHS-compliant package

–GK: 6/6 RoHS-compliant package

SigmaQuad-IIIe™ Family Overview

SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

Clocking and Addressing Schemes

The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are

synchronous devices. They employ dual, single-ended master

clocks, CK and CK. These clocks are single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. CK and CK are used to control the address and control

input registers, as well as all output timing.

The KD and KD clocks are dual mesochronous (with respect to

CK and CK) input clocks that are used to control the data input

registers. Consequently, data input setup and hold windows

can be optimized independently of address and control input

setup and hold windows.

Each internal read and write operation in a SigmaQuad-IIIe B4

ECCRAM is four times wider than the device I/O bus. An

input data bus de-multiplexer is used to accumulate incoming

data before it is simultaneously written to the memory array.

An output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IIIe B4 ECCRAM is always two address

pins less than the advertised index depth (e.g. the 4M x 18 has

1M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles, etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

Note: Please contact GSI for availability of 714 MHz devices.

Parameter Synopsis

Speed Bin

Operating Frequency

Data Rate (per pin)

Read Latency

-675

675 / 450 MHz

1350 / 900 Mbps

3.0 / 2.0

1.3V to 1.4V

-625

625 / 400 MHz

1250 / 800 Mbps

3.0 / 2.0

1.3V to 1.4V

-550

550 / 375 MHz

1100 / 750 Mbps

3.0 / 2.0

1.25V to 1.4V

-500

500 / 333 MHz

1000 / 666 Mbps

3.0 / 2.0

1.25V to 1.4V