전자부품 데이터시트 검색엔진 |
|
GS8673EQ18BGK-500I 데이터시트(PDF) 5 Page - GSI Technology |
|
GS8673EQ18BGK-500I 데이터시트(HTML) 5 Page - GSI Technology |
5 / 31 page GS8673EQ18/36BK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 5/2012 5/31 © 2011, GSI Technology MZT[1:0] Input Termination Mode Select—Selects the termination mode used for all terminated inputs. Must be tied High or Low. MZT[1:0] = 00: disabled. MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT). MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT). MZT[1:0] = 11: reserved. Input PZT[1:0] Input Termination Configuration Select—Selects which inputs are terminated. Must be tied High or Low. PZT[1:0] = 00: Write Data only. PZT[1:0] = 01: Write Data, Input Clocks. PZT[1:0] = 10: Write Data, Address, Control. PZT[1:0] = 11: Write Data, Address, Control, Input Clocks. Input MVQ I/O Voltage Select—Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low. MVQ = 0: Configure for 1.2V to 1.35V nominal VDDQ. MVQ = 1: Configure for 1.5V nominal VDDQ. Input VDD Core Power Supply—1.35V nominal core supply voltage. — VDDQ I/O Power Supply—1.2V to 1.5V nominal I/O supply voltage. Configurable via MVQ pin. — VREF Input Reference Voltage—Input buffer reference voltage. — VSS Ground — TCK JTAG Clock Input TMS JTAG Mode Select—Weakly pulled High internally. Input TDI JTAG Data Input—Weakly pulled High internally. Input TDO JTAG Data Output Output MCH Must Connect High—May be tied to VDDQ directly or via a 1kΩ resistor. Input MCL Must Connect Low—May be tied to VSS directly or via a 1kΩ resistor. Input NC No Connect—There is no internal chip connection to these pins. They may be left unconnected, or tied High or Low. — NUI Not Used, Input—There is an internal chip connection to these input pins, but they are unused by the device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied High. Input NUO Not Used, Output—There is an internal chip connection to these output pins, but they are unused by the device. Unused output pins are tri-stated internally. They should be left unconnected. Output Pin Description (Continued) Symbol Description Type |
유사한 부품 번호 - GS8673EQ18BGK-500I |
|
유사한 설명 - GS8673EQ18BGK-500I |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |