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GS8672Q38BE-400 데이터시트(PDF) 1 Page - GSI Technology

부품명 GS8672Q38BE-400
상세설명  On-Chip ECC with virtually zero SER
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
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GS8672Q20/38BE-500/450/400
72Mb SigmaQuad-II+TM
Burst of 2 ECCRAMTM
500 MHz–400 MHz
1.8 V VDD
1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.01c 8/2017
1/28
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• 2.5 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard package
• Dual Double Data Rate interface
• Byte Write Capability
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 36Mb and144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ ECCRAM Overview
The GS8672Q20/38BE are built in compliance with the
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)
ECCRAMs. The GS8672Q20/38BE SigmaQuad ECCRAMs
are just one element in a family of low power, low voltage
HSTL I/O ECCRAMs designed to operate at the speeds needed
to implement economical high performance networking
systems.
Clocking and Addressing Schemes
The GS8672Q20/38BE SigmaQuad-II+ ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B2 ECCRAM is always one address
pin less than the advertised index depth (e.g., the 4M x18 has
an 2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
Parameter Synopsis
-500
-450
-400
tKHKH
2.0 ns
2.2 ns
2.5 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns


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