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CDB61535A 데이터시트(PDF) 5 Page - Cirrus Logic |
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CDB61535A 데이터시트(HTML) 5 Page - Cirrus Logic |
5 / 44 page E1 SWITCHING CHARACTERISTICS (TA = -40 °C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 25) fc - 8.192000 - MHz TCLK Frequency ftclk -2.048 - MHz TCLK Duty Cycle for LEN2/1/0 = 0/0/0 (Note 32) tpwh2/tpw2 40 50 60 % ACLKI Frequency (Note 26) faclki -2.048 - MHz RCLK Duty Cycle (Note 27) tpwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 28) tr - - 85 ns Fall Time, All Digital Outputs (Note 28) tf - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 29) tsu1 100 194 - ns RDATA Valid Before RCLK Falling (Note 30) tsu1 100 194 - ns RPOS/RNEG Valid Before RCLK Rising (Note 31) tsu1 100 194 - ns RPOS/RNEG Valid After RCLK Falling (Note 29) th1 100 194 - ns RDATA Valid After RCLK Falling (Note 30) th1 100 194 - ns RPOS/RNEG Valid After RCLK Rising (Note 31) th1 100 194 - ns T1 SWITCHING CHARACTERISTICS (TA = -40 °C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 25) fc - 6.176000 - MHz TCLK Frequency ftclk -1.544 - MHz ACLKI Frequency (Note 26) faclki -1.544 - MHz RCLK Duty Cycle (Note 27) tpwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 28) tr - - 85 ns Fall Time, All Digital Outputs (Note 28) tf - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 29) tsu1 150 274 - ns RDATA Valid Before RCLK Falling (Note 30) tsu1 150 274 - ns RPOS/RNEG Valid Before RCLK Rising (Note 31) tsu1 150 274 - ns RPOS/RNEG Valid After RCLK Falling (Note 29) th1 150 274 - ns RDATA Valid After RCLK Falling (Note 30) th1 150 274 - ns RPOS/RNEG Valid After RCLK Rising (Note 31) th1 150 274 - ns Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 26. ACLKI provided by an external source or TCLK. 27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 28. At max load of 1.6 mA and 50 pF. 29. Host Mode (CLKE = 1). 30. Extended Hardware Mode. 31. Hardware Mode, or Host Mode (CLKE = 0) 32. The transmitted pulse width does not depend on the TCLK duty cycle. CS61577 DS155PP2 5 |
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