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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD7617 데이터시트(PDF) 7 Page - Analog Devices |
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AD7617 데이터시트(HTML) 7 Page - Analog Devices |
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7 / 52 page  AD7617 Data Sheet Rev. 0 | Page 6 of 51 TIMING SPECIFICATIONS Universal Timing Specifications VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance (CLOAD) of 30 pF, dependent on VDRIVE and load capacitance for serial interface (see Table 15). Table 2. Parameter1 Min Typ Max Unit Description tCYCLE 1 µs Minimum time between consecutive CONVST rising edges (excluding burst and oversampling modes) tCONV_LOW 50 ns CONVST low pulse width tCONV_HIGH 50 ns CONVST high pulse width tBUSY_DELAY 32 ns CONVST high to BUSY high (manual mode) tCS_SETUP 20 ns BUSY falling edge to CS falling edge setup time tCH_SETUP 50 ns Channel select setup time in hardware mode for CHSELx tCH_HOLD 20 ns Channel select hold time in hardware mode for CHSELx tCONV 475 520 ns Conversion time for the selected channel pair tACQ 480 ns Acquisition time for the selected channel pair tQUIET 50 ns CS rising edge to next CONVST rising edge tRESET_LOW Partial Reset 40 500 ns Partial RESET low pulse width Full Reset 1.2 µs Full RESET low pulse width tDEVICE_SETUP Partial Reset 50 ns Time between partial RESET high and CONVST rising edge Full Reset 15 ms Time between full RESET high and CONVST rising edge tWRITE Partial Reset 50 ns Time between partial RESET high and CS for write operation Full Reset 240 µs Time between full RESET high and CS for write operation tRESET_WAIT 1 ms Time between stable VCC/VDRIVE and release of RESET (see Figure 51) tRESET_SETUP Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 51) Partial Reset 10 ns Full Reset 0.05 ms tRESET_HOLD Time after release of RESET that queried hardware inputs must be stable for (see Figure 51) Partial Reset 10 ns Full Reset 0.24 ms 1 Not production tested. Sample tested during initial release to ensure compliance. Figure 2. Universal Timing Diagram Across All Interfaces CONVST BUSY CS CHx CHy CHSEL0 TO CHSEL2 t BUSY_DELAY t CONV_HIGH t QUIET t CS_SETUP t CH_SETUP t CH_HOLD HARDWARE MODE ONLY t CYCLE t CONV_LOW t CONV t ACQ |
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