전자부품 데이터시트 검색엔진 |
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AD9200ARS 데이터시트(PDF) 11 Page - Analog Devices |
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AD9200ARS 데이터시트(HTML) 11 Page - Analog Devices |
11 / 25 page AD9200 –10– REV. E SHA A2 10k 10k 10k A/D CORE 4.2k TOTAL REFTS REFBS 10 F 0.1 F REFTF REFBF 0.1 F AIN +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF –F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF 0.1 F MODE (AVDD) +FS –FS AD9200 10k a. Top/Bottom Mode V MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO MODE INTERNAL REF AVDD/2 SHA 10k 10k 10k A/D CORE 4.2k TOTAL 10 F 0.1 F REFTF REFBF 0.1 F AIN 0.1 F AD9200 10k A2 REFTS REFBS AVDD/2 c. Differential Mode A1 1V AVSS REFSENSE VREF (1V) AD9200 0.1 F 1.0 F d. 1 V Reference 0.01 F 1.0 F A1 10k 10k 1V AVSS REFSENSE VREF (2V) AD9200 e. 2 V Reference A1 1V AVSS REFSENSE VREF (= 1 + RA/RB) RA RB INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF RA AND RB. AD9200 0.1 F 1.0 F f. Variable Reference (Between 1 V and 2 V) Figure 16. A1 1V REFSENSE AVDD VREF AD9200 g. Internal Reference Disable (Power Reduction) MODE INTERNAL REF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF MIDSCALE V* AVDD/2 * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE 10k 10k 10k A/D CORE 4.2k TOTAL REFTS REFBS 10 F 0.1 F REFTF REFBF 0.1 F AIN 0.1 F AD9200 10k A2 SHA b. Center Span Mode |
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