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SN74AUP1G240YZPR 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 SN74AUP1G240YZPR
상세설명  Low-Power Single Inverter With 3-State Output
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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SN74AUP1G240YZPR 데이터시트(HTML) 4 Page - Texas Instruments

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SN74AUP1G240
SCES627D – MARCH 2005 – REVISED OCTOBER 2017
www.ti.com
Product Folder Links: SN74AUP1G240
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
4.6
V
VI
Input voltage(2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state(2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
Tj
Junction Temperature
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
1000
(1)
The A data input pins may be floated if the OE is high and the outputs are disabled; otherwise, all unused inputs of the device must be
held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs.
6.3 Recommended Operating Conditions
See
(1)
MIN
MAX
UNIT
VCC
Supply voltage
0.8
3.6
V
VIH
High-level input voltage
VCC = 0.8 V
VCC
3.6
V
VCC = 1.1 V to 1.95 V
0.65 × VCC
3.6
VCC = 2.3 V to 2.7 V
1.6
3.6
VCC = 3 V to 3.6 V
2
3.6
VIL
Low-level input voltage
VCC = 0.8 V
0
V
VCC = 1.1 V to 1.95 V
0
0.35 × VCC
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 3 V to 3.6 V
0
0.9
VO
Output voltage
Active state
0
VCC
V
3-state
0
3.6
Δt/Δv
Input transition rise or fall rate
VCC = 0.8 V to 3.6 V
200
ns/V
TA
Operating free-air temperature
–40
85
°C


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