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AD7142 데이터시트(PDF) 15 Page - Analog Devices

부품명 AD7142
상세설명  Programmable Controller for Capacitance Touch Sensors
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Data Sheet
AD7142
Rev. B | Page 15 of 70
CAPACITANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7142 has a Σ-Δ
architecture with 16-bit resolution. There are 14 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the control register, as listed in Table 9.
Table 9. CDC Decimation Rate
Decimation Bit Value
Decimation Rate
CDC Output Rate
Per Stage
00
256
3.072 ms
01
128
1.536 ms
101
111
1 Do not use this setting.
The decimation process on the AD7142 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3 times the
decimation rate. So 3 × 256 or 3 × 128 samples are averaged to
obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage, thus, a trade-off is possible
between a noise-free signal and speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7142 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
other source, such as connectors. In Figure 22, CIN is the
capacitance of the input sensors, and CBULK is the capacitance
between layers of the sensor PCB. CBULK can be offset using the
on-board DACs.
PLASTIC OVERLAY
SENSOR BOARD
CBULK
CIN
CAPACITIVE SENSOR
Figure 22. Capacitances Around the Sensor PCB
A simplified block diagram in Figure 23 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of ±20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.
POS_AFE_OFFSET
16-BIT
CDC
NEG_AFE_OFFSET
+DAC
(20pF RANGE)
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
7
7
16
CIN
SRC
CIN_CONNECTION_SETUP
REGISTER
–DAC
(20pF RANGE)
+
_
Figure 23. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7142 has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can
be performed in one sequence. Each of the 12 conversion stages
can measure the input from a different sensor. By using the
Bank 2 registers, each stage can be uniquely configured to support
multiple capacitance sensor interface requirements. For example,
a slider sensor can be assigned to STAGE1 through STAGE8,
with a button sensor assigned to STAGE0.
The AD7142 on-chip sequence controller provides conversion
control beginning with STAGE0. Figure 24 shows a block diagram
of the CDC conversion stages and CIN inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM register. Depen-
ding on the number and type of capacitance sensors that are
used, not all conversion stages are required. Use the SEQUENCE_
STAGE_NUM register to set the number of conversions in one
sequence, depending on the sensor interface requirements. For
example, this register would be set to 5 if the CIN inputs were
mapped to only six stages. In addition, set the STAGE_CAL_EN
registers according to the number of stages that are used.


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