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AD7143 데이터시트(PDF) 13 Page - Analog Devices |
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AD7143 데이터시트(HTML) 13 Page - Analog Devices |
13 / 57 page AD7143 Rev. 0 | Page 12 of 56 Complete Solution for Capacitance Sensing Analog Devices, Inc. provides a complete solution for capacitance sensing. The two main elements to the solution are the sensor PCB and the AD7143. If the application requires high resolution sensors, such as scroll bars or wheels, software is required that runs on the host processor. (No software is required for button sensors.) The memory requirements for the host depend upon the sensor, and are typically 9 kB of code and 600 bytes of data memory. AD7143 SENSOR PCB S1 S2 S3 S7 S6 S5 S4 S8 SRC 8 I2C HOST PROCESSOR 1 MIPS 9kB ROM 600 BYTES RAM Figure 18. Three Part Capacitance Sensing Solution Analog Devices supplies the sensor PCB footprint design libraries to the customer based on the customer’s specifications, and supplies any necessary software on an open-source basis. OPERATING MODES The AD7143 has three operating modes. Full power mode, where the device is always fully powered, is suited for applications where power is not a concern. One example is game consoles that have an ac power supply. Low power mode, where the part automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. In shutdown mode, the part shuts down completely. The POWER_MODE bits (Bit 0 and Bit 1) of the control register set the operating mode on the AD7143. The control register is at Address 0x000. Table 6 shows the POWER_MODE settings for each operating mode. To put the AD7143 into shutdown mode, set the POWER_MODE bits to either 01 or 11. Table 6. POWER_MODE Settings POWER_MODE Bits Operating Mode 00 Full power mode 01 Full shutdown mode 10 Low power mode 11 Full shutdown mode The power-on default setting of the POWER_MODE bits is 00, full power mode. Full Power Mode In full power mode, all sections of the AD7143 remain fully powered at all times. While a sensor is being touched, the AD7143 processes the sensor data. If no sensor is touched, the AD7143 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7143 converts at a constant rate. See the CDC Conversion Sequence Time section for more information. Low Power Mode When in low power mode, the AD7143 POWER_MODE bits are set to 10 upon device initialization. If the external sensors are not touched, the AD7143 reduces its conversion frequency, thereby greatly reducing its power consumption. The part remains in a reduced power state when the sensors are not touched. Every LP_CONV_DELAY ms (200 ms, 400 ms, 600 ms or 800 ms), the AD7143 performs a conversion and uses this data to update the compensation logic. When an external sensor is touched, the AD7143 begins a conversion sequence every 25 ms to read back data from the sensors. In low power mode, the total current consumption of the AD7143 is an average of the current used during a conversion, and the current used while the AD7143 is waiting for the next conversion to begin. For example, when LP_CONV_DELAY is 400 ms, the AD7143 typically uses 0.9 mA current for 25 ms and 15 μA for 400 ms of the conversion interval. Note that these conversion timings can be altered through the register settings. See the CDC Conversion Sequence Time section for more information. NO YES YES NO TIMEOUT AD7143 SETUP AND INITIALIZATION POWER_MODE = 10 ANY SENSOR TOUCHED? CONVERSION SEQUENCE EVERY LP_CONV_DELAY ms UPDATE COMPENSATION LOGIC DATA PATH PROXIMITY TIMER COUNT DOWN CONVERSION SEQUENCE EVERY 25ms FOR SENSOR READBACK ANY SENSOR TOUCHED? Figure 19. Low Power Mode Operation The time taken for the AD7143 to go from a full power state to a reduced power state, once the user stops touching the external sensors, is configurable. Once the sensors are not touched, the PWR_DWN_TIMEOUT bits, in the Ambient Compensation Ctrl 0 Register at Address 0x002, control the amount of time necessary for the device to return to a reduced power state. |
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