AD7156_17 datasheet(12/29 Pages) AD

부품명	AD7156

상세설명	2-Channel Capacitance Converter

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AD7156

Rev. 0 | Page 11 of 28

THEORY OF OPERATION

DIGITAL

FILTER

POWER-DOWN

TIMER

CLOCK

GENERATOR

SERIAL

INTERFACE

CIN1

CX1

CX2

EXC1

Σ-Δ CDC

CIN2

EXC2

MUX

EXCITATION

CAPDAC

THRESHOLD

SCL

VDD

GND

AD7156

SDA

PROGRAMMING

INTERFACE

DIGITAL

OUTPUTS

OUT1

OUT2

3.3V

Figure 22. AD7156 Block Diagram

The AD7156 core is a high performance capacitance-to-digital

converter (CDC) that allows the part to be interfaced directly

to a capacitive sensor.

The comparators compare the CDC results with thresholds, either

fixed or dynamically adjusted by the on-chip adaptive threshold

algorithm engine. Thus, the outputs indicate a defined change in

the input sensor capacitance.

The AD7156 also integrates an excitation source, CAPDAC

for the capacitive inputs, an input multiplexer, a complete clock

generator, a power-down timer, a power supply monitor, control

logic, and an I2C®-compatible serial interface for configuring the

part and accessing the internal CDC data and status, if required

in the system (see Figure 22).

CAPACITANCE-TO-DIGITAL CONVERTER

Figure 23 shows the CDC simplified functional diagram. The

converter consists of a second-order Σ-Δ charge balancing

modulator and a third-order digital filter. The measured

capacitance CX is connected between an excitation source

and the Σ-Δ modulator input. The excitation signal is applied

on the CX capacitor during the conversion, and the modulator

continuously samples the charge going through the CX. The

digital filter processes the modulator output, which is a stream

of 0s and 1s containing the information in 0 and 1 density. The

data is processed by the adaptive threshold engine and output

comparators; the data can also be read through the serial interface.

The AD7156 is designed for floating capacitive sensors.

Therefore, both CX plates have to be isolated from ground

or any other fixed potential node in the system.

The AD7156 features slew rate limiting on the excitation voltage

output, which decreases the energy of higher harmonics on the

excitation signal and dramatically improves the system electro-

magnetic compatibility (EMC).

DIGITAL

FILTER

0x0000 TO 0xFFF0

DATA

CLOCK

GENERATOR

CAPACITANCE-TO-DIGITAL CONVERTER

(CDC)

CIN

CX

0pF TO 4pF

EXC

EXCITATION

Σ-Δ

MODULATOR

Figure 23. CDC Simplified Block Diagram

CAPDAC

The AD7156 CDC core maximum full-scale input range is 0 pF

to 4 pF. However, the part can accept a higher input capacitance,

caused, for example, by a nonchanging offset capacitance of up to

10 pF. This offset capacitance can be compensated for by using

the programmable on-chip CAPDAC.

0x0000 TO 0xFFF0

DATA

CIN

EXC

CAPDAC

10pF

0pF TO 4pF

CX

10pF TO 14pF

Figure 24. Using a CAPDAC

The CAPDAC can be understood as a negative capacitance

connected internally to a CIN pin. The CAPDAC has a 6-bit

resolution and a monotonic transfer function. Figure 24 shows

how to use the CAPDAC to shift the CDC 0 pF to 4 pF input

range to measure capacitance between 10 pF and 14 pF.

유사한 부품 번호 - AD7156_17

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD7156BCPZ-REEL	533Kb / 28P	Ultralow Power, 1.8 V, 3 mm 횞 3 mm, 2-Channel Capacitance Converter REV. 0
Analog Devices	AD7156BCPZ-REEL7	533Kb / 28P	Ultralow Power, 1.8 V, 3 mm 횞 3 mm, 2-Channel Capacitance Converter REV. 0

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AD7156 데이터시트(PDF) 12 Page - Analog Devices

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유사한 부품 번호 - AD7156_17

유사한 설명 - AD7156_17

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