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AD7156 데이터시트(PDF) 6 Page - Analog Devices |
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AD7156 데이터시트(HTML) 6 Page - Analog Devices |
6 / 29 page AD7156 Rev. 0 | Page 5 of 28 TIMING SPECIFICATIONS VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments CONVERTER Conversion Time1 20 ms Both channels, 10 ms per channel. Wake-Up Time from Power-Down Mode2, 3 0.3 ms Power-Up Time2, 4 2 ms Reset Time2, 5 2 ms SERIAL INTERFACE6, 7 See Figure 2. SCL Frequency 0 400 kHz SCL High Pulse Width, tHIGH 0.6 μs SCL Low Pulse Width, tLOW 1.3 μs SCL, SDA Rise Time, tR 0.3 μs SCL, SDA Fall Time, tF 0.3 μs Hold Time (Start Condition), tHD;STA 0.6 μs After this period, the first clock is generated. Setup Time (Start Condition), tSU;STA 0.6 μs Relevant for repeated start condition. Data Setup Time, tSU;DAT 0.1 μs Setup Time (Stop Condition), tSU;STO 0.6 μs Data Hold Time (Master), tHD;DAT 10 ns Bus-Free Time (Between Stop and Start Conditions), tBUF 1.3 μs 1 Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion. 4 Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial interface command. 5 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface command. 6 Sample tested during initial release to ensure compliance. 7 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. P S tLOW tR tF tHD;STA tHD;DAT tSU;DAT tSU;STA tHD;STA tSU;STO tHIGH SCL PS SDA tBUF Figure 2. Serial Interface Timing Diagram |
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