전자부품 데이터시트 검색엔진 |
|
ADAV801 데이터시트(PDF) 43 Page - Analog Devices |
|
ADAV801 데이터시트(HTML) 43 Page - Analog Devices |
43 / 61 page ADAV801 Rev. A | Page 42 of 60 Interrupt Status—Address 0011100 (0x1C) Table 69. Interrupt Status Register Bit Map 7 6 5 4 3 2 1 0 SRCError TxCSTINT TxUBINT TxCSBINT RxCSDIFF RxUBINT RxCSBINT RxERROR Table 70. Interrupt Status Register Bit Descriptions Bit Name Description SRCError This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register. This bit remains high until the interrupt status register is read. TxCSTINT This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being copied from the transmitter CS buffer to the S/PDIF transmit buffer. TxUBINT This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read. TxCSBINT This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high until the interrupt status register is read. RxCSDIFF This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains high until read, but does not generate an interrupt. RxUBINT This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status register is read. RxCSBINT This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when RxBCONF3 = 1. This bit remains high until the interrupt status register is read. RxERROR This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver error register. This bit remains high until the interrupt status register is read. Interrupt Status Mask—Address 0011101 (0x1D) Table 71. Interrupt Status Mask Register Bit Map 7 6 5 4 3 2 1 0 SRCError Mask TxCSTINT Mask TxUBINT Mask TxCSBINT Mask Reserved RxUBINT Mask RxCSBINT Mask RxError Mask Table 72. Interrupt Status Mask Register Bit Descriptions Bit Name Description SRCError Mask Masks the SRCError bit from generating an interrupt. 0 = SRCError bit does not generate an interrupt. 1 = SRCError bit generates an interrupt. TxCSTINT Mask Masks the TxCSTINT bit from generating an interrupt. 0 = TxCSTINT bit does not generate an interrupt. 1 = TxCSTINT bit generates an interrupt. TxUBINT Mask Masks the TxUBINT bit from generating an interrupt. 0 = TxUBINT bit does not generate an interrupt. 1 = TxUBINT bit generates an interrupt. TxCSBINT Mask Masks the TxCSBINT bit from generating an interrupt. 0 = TxCSBINT bit does not generate an interrupt. 1 = TxCSBINT bit generates an interrupt. RxUBINT Mask Masks the RxUBINT bit from generating an interrupt. 0 = RxUBINT bit does not generate an interrupt. 1 = RxUBINT bit generates an interrupt. RxCSBINT Mask Masks the RxCSBINT bit from generating an interrupt. 0 = RxCSBINT bit does not generate an interrupt. 1 = RxCSBINT bit generates an interrupt. RxError Mask Masks the RxError bit from generating an interrupt. 0 = RxError bit does not generate an interrupt. 1 = RxError bit generates an interrupt. |
유사한 부품 번호 - ADAV801_17 |
|
유사한 설명 - ADAV801_17 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |