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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADAV801 데이터시트(PDF) 26 Page - Analog Devices |
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ADAV801 데이터시트(HTML) 26 Page - Analog Devices |
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26 / 61 page  ADAV801 Rev. A | Page 25 of 60 Table 10. Professional Audio Standard Data Bits Address1 7 6 5 4 3 2 1 0 N Sample Frequency Lock Emphasis Non- Audio Pro/Con = 1 N + 1 User Bit Management Channel Mode N + 2 Alignment Level Source Word Length Use of Auxiliary Mode Sample Bits N + 3 Channel Identification N + 4 fS Scaling Sample Frequency (fS) Reserved Digital Audio Reference Signal N + 5 Reserved N + 6 Alphanumeric Channel Origin Data—First Character N + 7 Alphanumeric Channel Origin Data N + 8 Alphanumeric Channel Origin Data N + 9 Alphanumeric Channel Origin Data—Last Character N + 10 Alphanumeric Channel Destination Data—First Character N + 11 Alphanumeric Channel Destination Data N + 12 Alphanumeric Channel Destination Data N + 13 Alphanumeric Channel Destination Data—Last Character N + 14 Local Sample Address Code—LSW N + 15 Local Sample Address Code N + 16 Local Sample Address Code N + 17 Local Sample Address Code—MSW N + 18 Time of Day Code—LSW N + 19 Time of Day Code N + 20 Time of Day Code N + 21 Time of Day Code—MSW N + 22 Reliability Flags Reserved N + 23 Cyclic Redundancy Check Character (CRCC) 1 N = 0x20 for receiver channel status buffer. N = 0x38 for transmitter channel status buffer. The standards allow the channel status bits in each subframe to be independent, but ordinarily the channel status bits in the two subframes of each frame are the same. The channel status bits are defined differently for the consumer audio standards and the professional audio standards. The 192 channel status bits are organized into 24 bytes and have the interpretations shown in Table 9 and Table 10. The S/PDIF transmitter and receiver have a comprehensive register set. The registers give the user full access to the functions of the S/PDIF block, such as detecting nonaudio and validity bits, Q subcodes, and preambles. The channel status bits as defined by the IEC60958 and AES3 specifications are stored in register buffers for ease of use. An autobuffering function allows channel status bits and user bits read by the receiver to be copied directly to the transmitter block, removing the need for user intervention. Receiver Section The ADAV801 uses a double-buffering scheme to handle read- ing channel status and user bit information. The channel status bits are available as a memory buffer, taking up 24 consecutive register locations. The user bits are read using an indirect memory addressing scheme, where the receiver user bit indirect-address register is programmed with an offset to the user bit buffer, and the receiver user bit data register can be read to determine the user bits at that location. Reading the receiver user bit data register automatically updates the indirect address register to the next location in the buffer. Typically, the receiver user bit indirect-address register is programmed to zero (the start of the buffer), and the receiver user bit data register is read repeatedly until all the buffer’s data has been read. Figure 46 and Figure 47 show how receiving the channel status bits and user bits is implemented. SECOND BUFFER RECEIVE CS BUFFER (0x20 TO 0x37) CHANNEL STATUS A (24 × 8 BITS) CHANNEL STATUS B (24 × 8 BITS) RxCSSWITCH DIRIN S/PDIF RECEIVE BUFFER FIRST BUFFER Figure 46. Channel Status Buffer S/PDIF 0...7 8...15 16...23 FIRST BUFFER 0...7 8...15 16...23 USER-BIT BUFFER ADDRESS = 0x50 ADDRESS = 0x51 RECEIVER USER BIT INDIRECT ADDRESS REGISTER RECEIVER USER BIT DATA REGISTER Figure 47. Receiver User Bit Buffer The S/PDIF receive buffer is updated continuously by the incoming S/PDIF stream. Once all the channel status bits for the block (192 for Channel A and 192 for Channel B) are received, the bits are copied into the receiver channel status buffer. This buffer stores all 384 bits of channel status information, and the RxCSSWITCH bit in the channel status switch buffer register determines whether the Channel A or the Channel B status bits are required to be read. The receive channel status bit buffer is 24 bytes long and spans the address range from 0x20 to 0x37. Because the channel status bits of an S/PDIF stream rarely change, a software interrupt/flag bit, RxCSBINT, is provided to notify the host control either that a new block of channel status bits is available or that the first five bytes of channel status information have changed from a previous block. The function of the RxCSBINT is controlled by the RxBCONF3 bit in the Receiver Buffer Configuration register. |
유사한 부품 번호 - ADAV801_17 |
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유사한 설명 - ADAV801_17 |
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