전자부품 데이터시트 검색엔진 |
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AD7171 데이터시트(PDF) 6 Page - Analog Devices |
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AD7171 데이터시트(HTML) 6 Page - Analog Devices |
6 / 17 page Data Sheet AD7171 Rev. C | Page 5 of 16 TIMING CHARACTERISTICS VDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted. Table 3. Parameter1, 2 Limit at TMIN, TMAX Unit Test Conditions/Comments READ t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width t33 0 ns min SCLK active edge to data valid delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t4 10 ns min SCLK inactive edge to DOUT/RDY high RESET t5 100 ns min PDRST low pulse width t6 25 ms typ PDRST high to data valid delay 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is the falling edge of SCLK. Timing Diagrams ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) ISOURCE (200µA WITH VDD = 5V, 100µA WITH VDD = 3V) 1.6V TO OUTPUT PIN 50pF Figure 2. Load Circuit for Timing Characterization t3 t1 t2 t4 DOUT/RDY (O) SCLK (I) I = INPUT, O = OUTPUT MSB LSB Figure 3. Read Cycle Timing Diagram t5 t6 PDRST (I) DOUT/RDY (O) I = INPUT, O = OUTPUT Figure 4. Resetting the AD7171 |
유사한 부품 번호 - AD7171_17 |
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유사한 설명 - AD7171_17 |
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