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54LS162ADMQB 데이터시트(PDF) 3 Page - National Semiconductor (TI) |
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54LS162ADMQB 데이터시트(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol Parameter Conditions Min Typ Max Units (Note 1) II Input Current Max VCC e Max VI e 7V Other 01 mA Input Voltage PE CET Inputs 02 IIH High Level Input Current VCC e Max VI e 27V Other 20 m A PE CET Inputs 40 IIL Low Level Input Current VCC e Max VI e 04V Inputs 54LS b 04 mA DM74 b 16 PE CET Inputs b 08 mA IOS Short Circuit VCC e Max 54LS b 20 b 100 mA Output Current (Note 2) DM74 b 20 b 100 ICCH Supply Current with VCC e Max PE e GND 31 mA Outputs HIGH CP e L Other Inputs e 45V ICCL Supply Current with VCC e Max VIN e GND 31 mA Outputs LOW CP e L Switching Characteristics VCC ea50V TA ea25 C RL e 2kX Symbol Parameter CL e 15 pF Units Min Max fmax Maximum Clock Frequency 25 MHz tPLH Propagation Delay 25 ns tPHL CP to TC 21 tPLH Propagation Delay 24 ns tPHL CP to Qn 27 tPLH Propagation Delay 14 ns tPHL CET to TC 23 tPHL Propagation Delay 28 ns MR to Qn (’160) Functional Description The ’LS160 and ’LS162 count modulo-10 in the BCD (8421) sequence From state 9 (HLLH) they increment to state 0 (LLLL) The ’161 and ’163 count modulo-16 binary se- quence From state 15 (HHHH) they increment to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs (except due to Master Reset of the ’LS160) occur as a re- sult of and synchronous with the LOW-to-HIGH transition of the CP input signal The circuits have four fundamental modes of operation in order of precedence asynchronous reset (’LS160) synchronous reset (’LS162) parallel load count-up and hold Five control inputsMaster Reset (MR ’LS160) Synchronous Reset (SR ’LS162) Parallel Enable (PE) Count Enable Parallel (CEP) and Count Enable Trickle (CET)determine the mode of operation as shown in the Mode Select Table A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP A LOW signal on PE overrides counting and allows informa- tion on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR (’LS160) or SR (’LS162) HIGH CEP and CET permit count- ing when both are HIGH Conversely a LOW signal on ei- ther CEP or CET inhibits counting The ’LS160A and ’LS162A use D-type edge-triggered flip- flops and changing the SR PE CEP and CET inputs when the CP is in either state does not cause errors provided that the recommended setup and hold times with respect to the rising edge of CP are observed 3 |
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