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SM65MLVD128DGGR 데이터시트(PDF) 7 Page - Texas Instruments |
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SM65MLVD128DGGR 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 16 page SN65MLVD128 SN65MLVD129 SLLS586 − MARCH 2004 www.ti.com 7 Output tpLH tpHL Input 0 V 0.9V V 0 V tf tr VCC VCC/2 0 V SS SS 0 V 0.1V SS SS VP(H) VP(L) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal A B R1 24.9 Ω tpZH tpHZ tpZL tpLZ VCC VCC/2 0 V ∼ 0.6 V 0.1 V 0 V ∼ −0.6 V 0 V −0.1 V EN Output With D at VCC Output GND or VCC EN Output With D at GND C1 1 pF R2 24.9 Ω C4 0.5 pF C2 1 pF D C3 2.5 pF Input NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B. C1, C2, C3, and C4 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T. Figure 6. Driver Enable and Disable Time Circuit and Definitions A B 0 V or VCC 1.62 k Ω, ±1% VA or VB Figure 7. Driver Maximum Steady State Output Voltage |
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