AD7980

Data Sheet

Rev. F | Page 6 of 26

−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 3.3 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

Throughput Rate

833

kSPS

Conversion Time: CNV Rising Edge to Data Available

500

800

ns

Acquisition Time

290

ns

Time Between Conversions

1.2

μs

CNV Pulse Width (CS Mode)

10

ns

SCK Period (CS Mode)

22

ns

SCK Period (Chain Mode)

23

ns

SCK Low Time

6

ns

SCK High Time

6

ns

SCK Falling Edge to Data Remains Valid

3

ns

SCK Falling Edge to Data Valid Delay

14

21

ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

18

40

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

20

ns

SDI Valid Setup Time from CNV Rising Edge

5

ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

10

ns

SDI Valid Hold Time from CNV Rising Edge (Chain Mode)

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

5

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

2

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

3

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

22

ns

Timing Diagrams

Figure 2. Load Circuit for Digital Interface Timing

Figure 3. Voltage Levels for Timing

500µA

500µA

1.4V

TO SDO

20pF

SPECIFICATIONS IN TABLE 3.