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MT9V024 데이터시트(PDF) 26 Page - ON Semiconductor |
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MT9V024 데이터시트(HTML) 26 Page - ON Semiconductor |
26 / 40 page MT9V024/D www.onsemi.com 26 Interlaced Readout The MT9V024 has two interlaced readout options. By setting R0x07[2:0] = 1, all the even−numbered rows are read out first, followed by a number of programmable field blanking rows (set by R0xBF[7:0]), then the odd−numbered rows, and finally the vertical blanking rows. By setting R0x07[2:0] = 2 only one field row is read out. Consequently, the number of rows read out is half what is set in the window height register. The row start register determines which field gets read out; if the row start register is even, then the even field is read out; if row start address is odd, then the odd field is read out. VALID IMAGE − Even Field 00 00 00 ………… 00 00 00 00 00 00 ………… 00 00 00 P4,1 P4,2 P4,3…………P4,n−1 P4,n P6,0 P6,1 P6,2…………P6,n−1 P6,n 00 00 00 …………………… 00 00 00 00 00 00 …………………… 00 00 00 00 00 00 ………… 00 00 00 00 00 00 ………… 00 00 00 00 00 00 ………… 00 00 00 00 00 00 ………… 00 00 00 Pm−2,0 Pm−2,2………Pm−2,n−2 Pm−2,n Pm,2 Pm,2…………Pm,n−1 Pm,n VALID IMAGE − Odd Field HORIZONTAL BLANKING FIELD BLANKING VERTICAL BLANKING P5,1 P5,2 P5,3…………P5,n−1 P5,n P7,0 P7,1 P7,2…………P7,n−1 P7,n Pm−3,1 Pm−3,2………Pm−3,n−1 Pm−3,n Pm,1 Pm,1…………Pm,n−1 Pm,n 00 00 00 ……………………………… 00 00 00 00 00 00 ……………………………… 00 00 00 Figure 34. Spatial Illustration of Interlaced Image Readout When interlaced mode is enabled, the total number of blanking rows are determined by both field blanking register (R0xBF) and vertical blanking register (R0x06). The followings are their equations. Field Blanking + R0xBF[7 : 0] (eq. 21) Vertical Blanking + R0x06[8 : 0] * R0xBF[7 : 0] (contextA) or R0xCE[8 : 0] * R0xBF[7 : 0] (contextB) (eq. 22) with minimum vertical blanking requirement + 4(absolute minimum operate; see Vertical Blanking Registers (eq. 23) description for VBlank minimums for valid image output) Similar to progressive scan, FV is logic LOW during the valid image row only. Binning should not be used in conjunction with interlaced mode. LINE_VALID By setting bit 2 and 3 of R0x72, the LV signal can get three different output formats. The formats for reading out four rows and two vertical blanking rows are shown in Figure 35. In the last format, the LV signal is the XOR between the continuous LV signal and the FV signal. Default FRAME_VALID LINE_VALID Continuously FRAME_VALID XOR FRAME_VALID LINE_VALID LINE_VALID Figure 35. Different LINE_VALID Formats |
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