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M41ST87W ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - STMicroelectronics

๋ถ€ํ’ˆ๋ช… M41ST87W
์ƒ์„ธ๋‚ด์šฉ  5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection
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M41ST87W ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - STMicroelectronics

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CLOCK OPERATION
The
eight
byte
clock
register
(see
Table
7., page 25) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Sec-
onds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
โ€œ00,โ€ and Tenths/Hundredths of Seconds cannot
be written to any value other than โ€œ00.โ€
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY Bit 0 (CB0)
and CENTURY Bit 1 (CB1). Bits D0 through D2 of
Register 04h contain the Day (day of week). Reg-
isters 05h, 06h, and 07h contain the Date (day of
month), Month, and Years. The ninth clock register
is the Control Register (this is described in the
Clock Calibration section). Bit D7 of Register 01h
contains the STOP Bit (ST). Setting this bit to a '1'
will cause the oscillator to stop. If the device is ex-
pected to spend a significant amount of time on
the shelf, the oscillator may be stopped to reduce
current drain. When reset to a '0' the oscillator re-
starts within one second (typical).
Note: A WRITE to ANY location within the first
eight bytes of the clock register (00h-07h), includ-
ing the OFIE Bit, CLRPW0 Bit, CLRPW1 Bit, THS
Bit, and so forth, will result in an update of the sys-
tem clock and a reset of the divider chain. This
could result in a significant corruption of the cur-
rent time, especially if the HT Bit (see โ€œPower
Down Time-Stampโ€ section) has not been previ-
ously reset. These non-clock related bits should
be written prior to setting the clock, and remain un-
changed until such time as a new clock time is also
written.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Power-Down Time-Stamp
Upon power-up following a power failure, the Halt
Update Bit (HT) will automatically be set to a '1.'
This will prevent the clock from updating the TIME-
KEEPERยฎ registers, and will allow the user to read
the time of the power-down event.
Note: When the HT Bit is set or a tamper event oc-
curs, the Tenths/Hundredths of a Second Register
(00h) will automatically be reset to a value of โ€œ00.โ€
All other date and time registers (01h - 07h) will re-
tain the value last updated prior to the power-down
or tamper event. The internal clock remains accu-
rate and no time is lost as a result of the zeroing of
the Tenth/Hundredths of a Second Register.
When updates are resumed (due to resetting the
HT Bit or TEB Bit), the correct time will be dis-
played.
Resetting the HT Bit to a '0' will allow the clock to
update the TIMEKEEPER registers with the cur-
rent time.
Note: If the TEB Bit is set, the Power Down Time-
Stamp will be disabled, and the Tamper Event
Time-Stamp will take precedence (see Tamper
Detection Operation, page 22).
TIMEKEEPERยฎ Registers
The M41ST87Y/W offers 22 internal registers
which contain Clock, Control, Alarm, Watchdog,
Flag, Square Wave, and Tamper data. The Clock
registers are memory locations which contain ex-
ternal (user accessible) and internal copies of the
data (usually referred to as BiPORTโ„ข TIMEKEEP-
ER cells). The external copies are independent of
internal functions except that they are updated pe-
riodically by the simultaneous transfer of the incre-
mented internal copy. The internal divider (or
clock) chain will be reset upon the completion of a
WRITE to any clock address (00h to 07h).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD format. Control, Watchdog and Square Wave
Registers store data in Binary Format.


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