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M41ST87W ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 32 Page - STMicroelectronics

๋ถ€ํ’ˆ๋ช… M41ST87W
์ƒ์„ธ๋‚ด์šฉ  5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection
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Power-fail Comparators (1 and 2)
Two Power-Fail Inputs (PFI1 and PFI2) are com-
pared to an internal reference voltage (1.25V). If
either PFI1 or PFI2 is less than the power-fail
threshold (VPFI), the associated Power-Fail Output
(PFO1 or PFO2) will go low. This function is intend-
ed for use as an under-voltage detector to signal a
failing power supply. Typically PFI1 and PFI2 are
connected through external voltage dividers (see
Figure 5., page 8) to either the unregulated DC in-
put (if it is available) or the regulated output of the
VCC regulator. The voltage divider can be set up
such that the voltage at PFI1 or PFI2 falls below
VPFI several milliseconds before the regulated
VCC input to the M41ST87Y/W or the microproces-
sor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO1 and PFO2 go (or remain) low.
This occurs after VCC drops below VPFD(min).
When power returns, PFO1 and PFO2 are forced
high, irrespective of VPFI for the write protect time
(trec), which is the time from VPFD(max) until the in-
puts are recognized. At the end of this time, the
power-fail comparator is enabled and PFO1 and
PFO2 follow PFI1 and PFI2. If the comparator is
unused, PFI1 or PFI2 should be connected to VSS
and the associated PFO1 or PFO2 left unconnect-
ed.
Power-fail Outputs
The PFO1 and PFO2 outputs are programmable
as N-channel, open drain output drivers, or full-
CMOS output drivers. By setting the Power-fail
Output Open Drain Bit (PFOD) to a '1,' the output
will be configured as open drain (with IOL as spec-
ified in Table 17., page 37). When PFOD is set to
'0,' the outputs will be configured as full-CMOS
(sink and source current as specified in Table
17., page 37).
Note: When configured as open drain (PFOD =
'1'), PFO1 and PFO2 will require an external pull-
up resistor.
Century Bits
These two bits will increment in a binary fashion at
the turn of the century, and handle leap years cor-
rectly. See Table 11., page 33 for additional expla-
nation.
Output Driver Pin
When the TIE Bit, OFIE Bit, AFE Bit, and watch-
dog register are not set to generate an interrupt,
the IRQ/OUT pin becomes an output driver that re-
flects the contents of D7 of the Control Register. In
other words, when D7 (OUT Bit) is a '0,' then the
IRQ/OUT pin will be driven low. With the ABE Bit
set to '1,' the OUT pin will continue to be driven low
in battery back-up.
Note: The IRQ/OUT pin is an open drain which re-
quires an external pull-up resistor.
Battery Low Warning
The M41ST87Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The battery may be re-
placed while VCC is applied to the device.
The M41ST87Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
trec Bit
Bit D7 of Clock Register 04h contains the trec Bit
(TR). trec refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This al-
lows for a voltage settling time before WRITEs
may again be performed to the device after a pow-
er-down condition. The trec Bit will allow the user to
set the length of this deselect time as defined by
Table 12., page 33.


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